1. Field of the Invention
The invention relates to a voltage generating method, and more particularly to a voltage converter.
2. Description of the Related Art
FIG. 1 shows a conventional buck converter. Referring to FIG. 1, the buck converter 1 generates a direct-current (DC) output voltage signal Vout and comprises an error amplifier 10, a compensating unit 11, a comparator 12, a driver 13, a P-type metal oxide semiconductor (PMOS) transistor 14, an NMOS transistor 15, an inductor 16, and a capacitor 17. The compensating unit 11 comprises a resistor 110 and a capacitor 111 coupled together in series between a node N10 and a signal ground GND. The PMOS transistor 14 and the NMOS transistor 15 are coupled in series between a supply voltage source VDD and the signal ground GND.
The error amplifier 10 receives the output voltage signal Vout and a reference voltage Vref and generates a control voltage signal Vc according to the difference between the output voltage signal Vout and the reference voltage Vref. The compensating unit 11 is charged or discharged by the control voltage signal Vc. The comparator 12 receives the control voltage signal Vc and a saw-wave signal Vramp and generates a pulse width modulation (PWM) signal Vpwm according to the difference between the control voltage signal Vc and the saw-wave signal Vramp. Referring to FIG. 2, an upper limit and a lower limit of a waveform of the saw-wave signal Vramp, which is applied to the conventional buck converter 1, are fixed, and the waveform of the saw-wave signal Vramp has only one slope within every period. It is assumed that the control voltage signal Vc is at a level LV10 in a stable state. According to the difference between the control voltage signal Vc at the level LV10 and the saw-wave signal Vramp, the PWM signal Vpwm generated thereby has a duty cycle D10. The driver 13 respectively switches ON/OFF states of the PMOS and NMOS transistors 14 and 15 according to the PWM signal Vpwm with the duty cycle D10. Accordingly, a square signal Vsqu is generated at a node N11. The square signal Vsqu is filtered by the inductor 16 and the capacitor 17, so that the DC output voltage signal Vout is generated at an output node Nout.
When an external load draws out a large current from the output node Nout, the level of the output signal Vout is pulled down due to the large current. At this time, referring to FIG. 2, the control voltage signal Vc is thus changed to a higher level LV11 according to the difference between the lowered output voltage signal Vout and the reference voltage Vref, so that the PWM signal Vpwm can have an increased duty cycle D11, which is larger than D10, for advantageous power transmission. In order to shorten the response time, the capacitor 111 generally has small capacitance. However, the capacitor 111 with small capacitance causes the control voltage signal Vc to have low stability, thus, resulting in an inaccurate output signal Vout being output.